specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. the products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appli ances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliab ility and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the intended use. if there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. 80112hk 20120531-s00007 no.a2080-1/24 ver1.0.0 LC786960E overview the LC786960E integrates arm7tdmi-s?, cd servo cont rol, cd signal processing, compressed audio decode processing, audio signal processing, usb host processing, sd memory card host processing and a flash memory to store the program for arm7tdmi-s? and various data in a package. furthermore, various kinds of interface functions such as sio, uart etc. reduce the external main controller?s processing load and make high performance and much functional cd player system, using with less components. features ? rf signal processing for cd-da/r/rw, servo control, and efm signal processing ? mp3*, wma*, aac* decoder processing ? sampling rate convertor, high frequency compensation filter and other various audio signal processing ? usb host function (full speed as 12mbps), sd memory card host function ? arm7tdmi-s? as internal cpu core, flash me mory for program and various data storage ? operating voltage: 3.3v typical ? operating temperature: -40 ? c to +85 ? c ? packages: qip100e (14 ? 20) ordering number : ena2080 cmos lsi compact disc player ic is a registered trademark of arm limited. * mp3(mpeg layer-3 audio coding) mpeg layer-3 audio coding technology li censed from fraunhofer iis and thomson. supply of this product does not convey license under the releva nt intellectual property of thomson and/or fraunhofer gesellscha ft nor imply any right to use this product in any finished end user or ready- to-use final product. an independent license for such use is r equired. for details, please visit http://mp3licensing.com/ . * windows media audio windows media tm is a trademark and a registered trademark in the united states and other countries of united states microsoft corporation. * aac advanced audio coding * this product incorporates technology licensed from silicon storage technology inc.
LC786960E no.a2080-2/24 detail of functions ? cd dsp functions ? ? playback mode: clv playback/jitter free playback (vcec) ? playback speed: normal speed, double speed ? rf system: agc, cd-r and cd-r/w playback support, peak hold, bottom hold ? error system: te signal generation, fe signal generation ? detection: track count signal, jitter, defect (black, mirror) ? laser power controller (apc) ? dc offset voltage cancellation ? all servo systems as tracking, focus, sled and spindle are implemented with digital processing. ? automatic adjustment functions: focus gain, focus bias, focus offset, tracking gain, tracking offs et and tracking balance ? shock detection / interruption detection ? efm signal synchronization detection, protection and interpolation ? error detection, correction (c1=double, c2=quadruple/double) ? jitter margin 19 frames ? buffers cd-text data ? starts buffering desired id3/id4 of cd-text data. ? cd-rom decoding (mode1, mode2 ) ? outputs cd-rom decoded data ? compressed audio decode functions ? ? mp3 decode (iso/iec 11172-3, iso/iec 13818-3) sampling rate support: mpeg1-layer1/2/3 (32khz, 44.1khz, 48khz) mpeg2-layer1/2/3 (16khz, 22.05khz, 24khz) mpeg2.5-layer3 ( 8khz, 11.025khz, 12khz) bit rate support: all bit rate (variable bit rate support) mpeg header read support ? wma decode (version 9 standard) sampling rate support: 8khz, 11.025khz, 16khz, 22.05khz, 32khz, 44.1khz, 48khz bit rate support: 5kbps to 384kbps (variable bit rate support) ? aac decode (iso/iec 14496-3, iso/iec 13818-7) profile: mpeg4-aac-lowcomplexity sampling rate support: 8khz, 11.025khz, 12khz, 16khz, 22.05khz, 24khz, 32khz, 44.1khz, 48khz bit rate support: monaural 8kbps to 160kbps (variable bit rate support) stereo 16kbps to 320kbps (variable bit rate support) ? decodes both the compressed data read from the di sc and input from outside through the interface pins
LC786960E no.a2080-3/24 ? audio processing functions ? ? sampling rate converter (src) for compressed audio data playback ? high frequency compensation filter for compressed audio data playback ? interpolation (cd-da only) ? mute function (-12db, - ) ? digital attenuator ? de-emphasis filter ? bilingual function ? bass / treble filter ? eight-fold over-sampling digital filter (24bit) ? one bit dac (tertiary ?? noise shaper type) ? secondary lpf for audio output ? allows external audio data supply to the dig ital filter and d/a converter (uses four signals) ? various external audio data output format iis (48fs/64fs), msb first right justified (32fs/48fs/64fs), 16 bit data length ? external interface functions ? ? open host controller interface 1.0a ? universal serial bus specification 1.1 supports up to full speed (12mhz)for usb2.0 ? supports four kinds of transfer type (control/bulk/interrupt/isochronous) ? multimedia card specification v2.11 ? secure digital memory card physical layer specification v0.96 * individual contract is necessary to use sd memory card controller. for detail, please contact to us. ? internal microcontroller functions ? ? cd, usb, sd memory card playback control servo control, cd-rom/usb/sd file analysis, etc. ? communication format: sio ? gpio port 27ports maximum (shared with other functions. several pins are 5v tolerant.) ? external interrupt pins 4pins maximum (shared with other functions.) ? serial interface sio clock synchronized full duplex (3 lines) 2 channel uart full duplex 2 channel iic master function 1 channel ? flash memory program version up from the external media (c d-rom/usb)or main controller is available. ? watch dog timer notify to outside from the pin or reset internally. ? power management 2 kinds of sleep mode (1) only cpu core operates at slow clock and clocks for other blocks are stopping. (2) all clocks are stopping. ? others ? ? 1.5v regulator for internal blocks
LC786960E no.a2080-4/24 specifications absolute maximum ratings at ta = 25 ? c, dv ss = av ss = lrv ss = xv ss 1 = xv ss 2 = vv ss 1 = vv ss 2 = 0v parameter symbol pin names conditions ratings unit maximum supply voltage v dd max dv dd , av dd , lrv dd , xv dd 1, xv dd 2, uv dd , vv dd 1, vv dd 2, vv dd 3 -0.3 to +3.95 v input voltage 1 v in 1 input pins other than v in 2 -0.3 to dv dd +0.3 v input voltage 2 v in 2 resb, sifck, sifdi, sifdo, sifce, busyb, gp03, gp04, gp05, gp06, gp07, gp10, gp11, gp12, jtrstb, jtck, jtdi, jtms -0.3 to +5.6 v output voltage v out -0.3 to dv dd +0.3 v allowable power dissipation pd max ta ? 85 ? c mounted reference pcb (*) 519 mw operating temperature topr -40 to +85 ? c storage temperature tstg -40 to +125 ? c (*)reference pcb: 114.3mm76.1mm1.6mm, glass epoxy resin allowable operating ranges at ta = -40 to +85 ? c, dv ss = av ss = lrv ss = xv ss 1 = xv ss 2 = vv ss 1 = vv ss 2 = 0v parameter symbol pin names conditions min typ max unit supply voltage v dd 1 dv dd , av dd , lrv dd , xv dd 1, xv dd 2, uv dd , vv dd 1, vv dd 2, vv dd 3 3.00 3.60 v high-level input voltage v ih (1) resb, sifck, sifdi, sifdo, sifce, busyb, gp03, gp04, gp05, gp06, gp07, gp10, gp11, gp12, jtms, jtrstb, jtck, jtdi schmitt 2.00 5.50 v v ih (2) gp13, gp30, gp31, gp32, gp33, gp34, gp35, gp36, gp37, gp43, gp44, gp45, gp50, gp51, gp52, gp53 schmitt 2.00 v dd 1v low-level input voltage v il (1) resb, sifck, sifdi, sifdo, sifce, busyb, gp03, gp04, gp05, gp06, gp07, gp10, gp11, gp12, jtms, jtrstb, jtck, jtdi schmitt 0 0.80 v v il (2) gp13, gp30, gp31, gp32, gp33, gp34, gp35, gp36, gp37, gp43, gp44, gp45, gp50, gp51, gp52, gp53, mode0, mode1, mode2 schmitt 0 0.80 v crystal oscillator frequency fx1 xin oscillator circuit 12.0 mhz xout fx2 x16in oscillator circuit 16.9344 mhz x16out
LC786960E no.a2080-5/24 electrical characteristics at ta = -40 to +85 ? c, v dd 1 = 3.0v to 3.6v, dv ss = av ss = lrv ss = xv ss 1 = xv ss 2 = vv ss 1 = vv ss 2 = 0v parameter symbol pin names conditions min typ max unit current drain i dd 1 dv dd , av dd , lrv dd , xv dd 1, xv dd 2, uv dd , vv dd 1, vv dd 2, vv dd 3 125 144 ma high-level input current i ih (1) resb, sifck, sifdi, jtms, jtrstb, jtck, jtdi, sifdo, sifce, busyb, gp03, gp04, gp05, gp06, gp07, gp10, gp11, gp12 schmitt, v in = 5.50v built-in pull-down resistor off 10.00 ? a i ih (2) gp13, gp30, gp31, gp32, gp33, gp34, gp35, gp36, gp37, gp43, gp44, gp45, gp50, gp51, gp52, gp53 schmitt, v in = v dd 1 built-in pull-down resistor off 10.00 ? a low-level input current i il (1) resb, sifck, sifdi, sifdo, sifce, busyb, gp03, gp04, gp05, gp06, gp07, gp10, gp11, gp12, gp13, gp30, gp31, gp32, gp33, gp34, gp35, gp36, gp37, gp43, gp44, gp45, gp50, gp51, gp52, gp53, jtms, jtrstb, jtck, jtdi, mode0, mode1, mode2 schmitt, v in = 0v -10.00 ? a high-level output voltage v oh (1) gp04, gp05, gp06, gp07, gp12, gp13, gp30, gp31, gp32, gp33, gp34, gp35, gp36, gp37, gp43, gp44, gp50, gp51, gp52, gp53 cmos, i oh = -2ma v dd 1-0.6 v v oh (2) sifdi, sifdo, sifce, busyb, gp03, gp10, gp11, gp45, jtdo, jtrtck cmos, i oh = -4ma v dd 1-0.6 v low-level output voltage v ol (1) gp04, gp05, gp06, gp07, gp12, gp13, gp30, gp31, gp32, gp33, gp34, gp35, gp36, gp37, gp43, gp44, gp50, gp51, gp52, gp53 cmos, i ol = 2ma 0.40 v v ol (2) sifdi, sifdo, sifce, busyb, gp03, gp10, gp11, gp45, jtdo, jtrtck cmos, i ol = 4ma 0.40 v output off-leakage current ioff(1) pdout0, pdout1, afilt hi-z out -10.00 10.00 ? a ioff(2) sifdo hi-z out -10.00 10.00 ? a built-in pull down resistor rp d sifdo, sifce, busyb, gp03, gp04, gp05, gp06, gp07, gp10, gp11, gp12, gp13, gp30, gp31, gp32, gp33, gp34, gp35, gp36, gp37, gp43, gp44, gp45, gp50, gp51, gp52, gp53 50 100 200 k ? charge pump output current ipdoh pdout1, pdout0 pckist = 100k ? current value setting: 1x 42.50 50.00 57.50 ? a ipdol pdout1, pdout0 -57.50 -50.00 -42.50 ? a iafilh afilt 15.0 ? a iafill afilt 15.0 ? a ? put a internal pull down resistor or external pull down resi stor or external pull up resistor to the sifdo pin if its output condition is set to 3-state mode.
LC786960E no.a2080-6/24 package dimensions unit : mm (typ) 3151a sanyo : qip100e(14x20) 20.0 23.2 14.0 17.2 0.15 0.8 (2.7) 3.0max 0.1 0.3 0.65 (0.58) 130 80 51 31 50 100 81
LC786960E no.a2080-7/24 pin assignment top view 30 29 vvss1 28 pckist 27 p cncnt 26 pdout0 25 pdout1 24 vvdd1 23 spdo 22 sldo 21 tdo 20 fdo 19 av d d 18 avss 17 lds 16 ldd 15 tein 14 fin 13 ein 12 jittc 11 vref 10 rfmon 9 s lciset 8 din 7 bin 6 cin 5 ain 4 phlpf 3 lpf 2 rfout 1 efmin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 lc786960 mode2 jtrstb jtck jtdi jtms jtdo jtrtck dvdd dvss dvdd15 xvss2 x16out x16in xvdd2 lrvdd lcho lrref rcho lrvss slco te gp34 gp35 gp36 gp37 mode0 mode1 dvdd dvss resb sifck sifdi sifdo sifce busyb gp03 gp05 gp06 gp07 xvdd1 xin xou t xvss1 udm udp uvdd vvdd2 vvss2 afilt vvdd3 gp04 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 81 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 50 gp33 gp32 gp31 gp30 gp53 gp52 gp51 gp50 dvdd15 dvss dvdd gp45 gp44 gp43 dvss dvdd gp13 gp12 gp 11 gp10
LC786960E no.a2080-8/24 pin description pin no. pin name i/o state when "reset" function 1 efmin ai input rf signal input 2 rfout ao undefined rf signal output 3 lpf ao undefined rf signal dc level detecti on low-pass filter capacitor connection 4 phlpf ao undefined defect detection low-pass filter capacitor connection 5 ain ai input a signal input 6 cin ai input c signal input 7 bin ai input b signal input 8 din ai input d signal input 9 slciset ai input slco output cu rrent setting resistor connection 10 rfmon ao undefined ic internal analog signal monitor 11 vref ao av dd /2 vref voltage output 12 jittc ao undefined jitter detection capacitor connection 13 ein ai input e signal input 14 fin ai input f signal input 15 te ao undefined te signal output 16 tein ai input te signal input used for tes signal generation 17 ldd ao undefined laser power control signal output 18 lds ai input laser power detection signal input 19 av ss - - analog system ground. this pin must be connected to the 0v level. 20 av dd - - analog system power supply 21 fdo ao av dd /2 focus control signal output 22 tdo ao av dd /2 tracking control signal output 23 sldo ao av dd /2 sled control signal output 24 spdo ao av dd /2 spindle control signal output 25 vv dd 1 - - efmpll power supply 26 pdout1 ao undefined efmpll charge pump output 1 27 pdout0 ao undefined efmpll charge pump output 0 28 pcncnt ai input efmpll charge pump control voltage input 29 pckist ai input efmpll charge pump current setting resistor connection pin 30 vv ss 1 - - efmpll ground. this pin must be connected to the 0v level. 31 gp10 i/o input (l) general purpose i/o port with pull down resistor uart1 data transmit 32 gp11 i/o input (l) general purpose i/o port with pull down resistor uart1 data receive 33 gp12 i/o input (l) general purpose i/o port with pull down resistor clock control input 1 34 gp13 i/o input (l) general purpose i/o port with pull down resistor clock control input 2 35 dv dd - - digital system power supply 36 dv ss - - digital system ground. this pin must be connected to the 0v level. 37 gp43 i/o input (l) general purpose i/o port with pull down resistor 38 gp44 i/o input (l) general purpose i/o port with pull down resistor 39 gp45 i/o input (l) general purpose i/o port with pull down resistor 40 dv dd - - digital system power supply 41 dv ss - - digital system ground. this pin must be connected to the 0v level. 42 dv dd 15 ao high capacitor connection pin for internal regulator 43 gp50 i/o input (l) general purpose i/o port with pull down resistor 44 gp51 i/o input (l) general purpose i/o port with pull down resistor 45 gp52 i/o input (l) general purpose i/o port with pull down resistor 46 gp53 i/o input (l) general purpose i/o port with pull down resistor continued to the next page.
LC786960E no.a2080-9/24 continued from the previous page. pin no. pin name i/o state when "reset" function 47 gp30 i/o input (l) general purpose i/o port with pull down resistor 48 gp31 i/o input (l) general purpose i/o port with pull down resistor 49 gp32 i/o input (l) general purpose i/o port with pull down resistor data 1 input/output for sd memory card 50 gp33 i/o input (l) general purpose i/o port with pull down resistor data 0 input/output for sd memory card 51 gp34 i/o input (l) general purpose i/o port with pull down resistor clock output for sd memory card 52 gp35 i/o input (l) general purpose i/o port with pull down resistor command input/output for sd memory card 53 gp36 i/o input (l) general purpose i/o port with pull down resistor data 3 input/output for sd memory card 54 gp37 i/o input (l) general purpose i/o port with pull down resistor data 2 input/output for sd memory card 55 mode0 i input lsi mode set pin 0 this pin must be connected to the 0v level. 56 mode1 i input lsi mode set pin 1 this pin must be connected to the 0v level. 57 dv dd - - digital system power supply 58 dv ss - - digital system ground. this pin must be connected to the 0v level. 59 resb i - ic reset input ("l"-active) this pin must be set low once after power is first applied. 60 sifck i input host-i/f data transmit clock input for serial communication 1 61 sifdi i/o input host-i/f data input for serial communication 1 62 sifdo i/o input host-i/f data output for serial communication 1 (cmos or 3-state output) 63 sifce i/o input host -i/f enable signal input for serial communication 1 ("h"-active) 64 busyb i/o input (l) host -i/f system busy signal output ("l"-active) 65 gp03 i/o input (l) general purpose i/o port with pull down resistor usb device detection flag output 66 gp04 i/o input (l) general purpose i/o port with pull down resistor iic (master) clock output 67 gp05 i/o input (l) general purpose i/o port with pull down resistor iic (master) data input/output 68 gp06 i/o input (l) general purpose i/o port with pull down resistor 69 gp07 i/o input (l) general purpose i/o port with pull down resistor 70 xv dd 1 - - oscillator power supply 71 xin i oscillation 12mhz oscillator connection 72 xout o oscillation 12mhz oscillator connection 73 xv ss 1 - - oscillator ground. this pin must be connected to the 0v level. 74 udm i/o - usb data input/output d- signal connection 75 udp i/o - usb data input/output d+ signal connection 76 uv dd - - usb power supply 77 vv dd 2 - - system pll power supply 78 vv ss 2 - - system pll ground. this pin must be connected to the 0v level. 79 afilt ao undefined audio pll charge pump output 80 vv dd 3 - - audio pll power supply 81 mode2 i input lsi mode set pin 2 this pin must be connected to the 0v level. continued to the next page.
LC786960E no.a2080-10/24 continued from the previous page. pin no. pin name i/o state when "reset" function 82 jtrstb i input jtag reset input (connect to pll-down resister or 0v level in normal mode.) 83 jtck i input jtag clock input (connect to pll-down resister or 0v level in normal mode.) 84 jtdi i input jtag data input (connect to pll-down resister or 0v level in normal mode.) 85 jtms i input jtag mode input (connect to pll-up resister or dv dd level in normal mode.) 86 jtdo o low jtag data output (leave open in normal mode.) 87 jtrtck o low jtag return clock output (leave open in normal mode.) 88 dv dd - - digital system power supply 89 dv ss - - digital system ground. this pin must be connected to the 0v level. 90 dv dd 15 ao high capacitor connection pin for internal regulator 91 xv ss 2 - - oscillator ground. this pin must be connected to the 0v level. 92 x16out o oscillation 16.9344mhz oscillator connection 93 x16in i oscillation 16.9344mhz oscillator connection 94 xv dd 2 - - oscillator power supply 95 lrv dd - - audio lpf power supply 96 lcho ao lrv dd /2 audio lch data output 97 lrref ao lrv dd /2 reference voltage for audio lpf 98 rcho ao lrv dd /2 audio rch data output 99 lrv ss - - audio lpf ground. this pin must be connected to the 0v level. 100 slco ao undefined slice level control output (1) for unused pins: ? the unused input pins must be connected to the gnd (0v) level if there is no individual note in the above table. ? the unused output pins must be left open (no connection) if there is no individual note in the above table. ? the unused input/output pins must be connected to the gnd (0v) or power supply pin for i/o block with internal pull down resistor off or be left open with internal pull down resistor on when input pin mode or must be left open (no connection) when output pin mode if there is no individual note in the above table. when you connect an i/o pin which is an input pin withou t internal pull-down resistor at reset mode to the gnd or power supply level, we recommend you to use pull-down resistor or pull-up resistor individually as fail-safe. (2) for power supply pins: ? same voltage level must be supplied to dv dd , av dd , xv dd 1, xv dd 2, vv dd 1, vv dd 2, vv dd 3, uv dd and lrv dd power supply pins. (refer to?allowable operating ranges?.) (3) for ?reset? condition: ? this lsi is not reset only by making the resb pin ?low?. refer to ?power on and reset contro l? for detail of ?reset? condition.
LC786960E no.a2080-11/24 block diagram buffer sram data trans controller mp3/wma/aac decoder audio control deemphasis/ mute/att external-in/out 8fs digital filter 1bit dac analog lpf interrupt uart iic sio gpio cdrom decoder cdtext decoder bufram i/f audio data-i/f src & hfc-filter usb host controller work ram boot rom watchdog timer cd pll usb-i/f flash memory host-i/f (sio/iic) x?tal-2 (16.9344mhz) x?tal-1 (12mhz) apll syspll regulator cd rf signal processor ad/da sd memory card controller cd servo controller arm7 core cache cd efm/ecc decoder 1.5v 3.3v
LC786960E no.a2080-12/24 power on and reset control ? attention when power on the resb pin must be set to ?low? level to initialize the operating state of internal flash memory. if the power is on during the resb pin is ?high? level, th is lsi may operate incorrectly because the internal flash memory is not initialized. in this case, this lsi is not initialized even if a low level supplied to resb pin. therefore, the resb pin must be set to ?low? level when power is first supplied. you may input the voltage of 3.6v or less to each input pin when the power supply is off. however, it is necessary to supply a regulated voltage to the power supply pin before hand when more than 3.6v voltage is input to the 5v tolerant input pins. power on/power down/reset timing vbot tpwd tresw1 tresw2 3.3v power v dd 1 3.3v power v dd 1 resb 0v power on stage during normal operation (oscillation clock is valid) parameter symbol min typ max unit power down time tpwd 10 ms power down voltage vbot 0 0.2 v reset time (power on) tresw1 20 ms reset time (normal) (*1) tresw2 1 ms *1: the specification of tresw2 above is the time defined while steady the x16 clock and having oscillated. when the x16 clock has been stopped by the command etc. , the specification of tresw2 could be larger than the value shown above, because it takes time that the x16 oscillator becomes stable.
LC786960E no.a2080-13/24 host interface the data transmission between this lsi and host controller is performed with spi type synchronous sio protocol. the transmission procedure is as follows. ? refer to the internal software speci fication of this lsi about m5 to m0 code in mode code transmission. when the input data of m5 to m0 coincide to the data in the internal register, the sifdo pin becomes to ?low? level (ack) then the transmission is enabled. when not coincide, the sifdo pin keeps ?high? level (nack) then the transmission is not enabled. ? the seventh data in mode code transmission shows whether the following procedure is the command transmission or the data reception. when the seventh data is ?low ?, the following procedure is command transmission. when the seventh data is ?high?, the following procedure is data reception. ? attention because the specifications of transmission timings are different depending on the internal cpu?s operating speed modes (low speed or normal speed). refer to the table in next page. communication interface format between host controller sifce mode (send) command 1 command 2 command n mode (receive) data 1 data 2 data n sifck sifdi sifdo busyb ack ack transmission/reception format between host controller (1) host: command transmission (2) host: data reception sifce 1 8 m5 m2 m4 m3 mode code byte 1st-data byte last-data byte nack ack m0 wr m1 d7 d2 d6 d5 d0 d1 2345678123 67 1 8 m5 m2 m4 m3 mode code byte 1st-data byte last-data byte nack ack m0 rd m1 d7 d2 d6 d5 d0 d1 2345678123 67 sifck sifdi sifdo busyb sifce sifck sifdi sifdo busyb
LC786960E no.a2080-14/24 communication timing specification between host controller sifce (input) sifck (input) sifdi (input) sifdo (output) busyb (output) tcdon tcdoh tcbst tcras tcdof tce tchd tckl tcwsu tcwhd tckh tcsu 1/fclk parameter symbol pin names min typ max unit sifck clock frequency fclk sifck 3.3 0.725 mhz sifck clock "h" level width tckh sifck 150 690 ns sifck clock "l" level width tckl sifck 150 690 ns transfer start enable time tce busyb, sifce 0 0 ns setup time for transfer start tcsu sifce, sifck 100 200 ns hold time for transfer end tchd sifce, sifck 100 200 ns setup time for sifdi tcwsu sifdi, sifck 75 75 ns hold time for sifdi tcwhd sifdi, sifck 75 200 ns output delay time for sifdo ?h? tcdoh sifdo, sifck 100 350 ns output delay time for sifdo tcras sifdo, sifck 100 350 ns turn on time for sifdo *1 tcdon sifdo, sifce 100 100 ns turn off time for sifdo *1 tcdof sifdo, sifce 150 150 ns busyb "l" level output delay time tcbst busyb 150 350 ns internal cpu operating speed m ode upper step : normal speed lower step : low speed * 1: the tcdon and tcdof specifications are for wh en the sifdo pin is set to the 3-state mode.
LC786960E no.a2080-15/24 usb specification at ta = -40 ? c to +85 ? c, v dd 1 = 3.0v to 3.6v, dv ss = av ss = lrv ss = xv ss 1 = xv ss 2 = vv ss 1 = vv ss 2 = 0v parameter symbol pin names conditions min typ max unit high-level input voltage v ih (usb) udm, udp 2.0 v low-level input voltage v il (usb) 0.8 input leakage current ili output driver: off -10.0 10.0 ? a differential input sensitivity vdi |(udp) - (udm)| 0.2 v common mode voltage range vcm includes vdi range 0.8 2.5 v high-level output voltage v oh (usb) connect 15k ? 5% pull-down resistor to gnd (0v). 2.8 3.6 v low-level output voltage v ol (usb) connect 1.5k ? 5% pull-up resistor to v dd 1. 0 0.3 v crossover voltage vcr 1.3 2.0 v usb data rising time tur cl = 50pf 4.0 20.0 ns usb data falling time tuf 4.0 20.0 example circuit for usb application * the value of resistors and capacitors in this circuit might be needed to be adjusted for each application. lc786960 v dd 1 uv dd udp udm 5pf 15k 15 5pf 15k 15
LC786960E no.a2080-16/24 sd memory card interface sd memory card input/output timing specification tsdckl tsdcms tsdcds tsdcmh tsdcmo tsdcdh tsdcdo sdcclk (output) sdcmdio (inout) sdcdat[3:0] (inout) tsdckh 1/fsdckf * relationship between signal name and pin name sdcclk : gp34 sdcmdio : gp35 sdcdat [3] : gp36 sdcdat [2] : gp37 sdcdat [1] : gp32 sdcdat [0] : gp33 parameter symbol pin names min typ max unit sdcclk clock frequency fsdckf sdcclk 6.0 mhz sdcclk clock "h" level width tsdckh sdcclk 83.3 ns sdcclk clock "l" level width tsdckl sdcclk 83.3 ns setup time for command input tsdcms sdcmdio, sdcclk 30.0 ns hold time for command input tsdcmh sdcmdio, sdcclk 30.0 ns command output valid time tsdcmo sdcmdio, sdcclk 30.0 ns setup time for data input tsdcds sdcdat [3:0], sdcclk 30.0 ns hold time for data input tsdcdh sdcdat [3:0], sdcclk 30.0 ns data output valid time tsdcdo sdcdat [3:0], sdcclk 30.0 ns note: internal cpu (arm7) must be set to normal mode. never use the sd memory card interface at the internal cpu?s low speed mode.
LC786960E no.a2080-17/24 internal voltage regulator at ta = -40 ? c to +85 ? c, dv ss = av ss = lrv ss = xv ss 1 = xv ss 2 = vv ss 1 = vv ss 2 = 0v parameter symbol condition min typ max unit output voltage dv dd 15 v dd 1 = 3.0v to 3.6v 1.35 1.50 1.65 v load current iope v dd 1 = 3.3v 200 ma note : the spec. of ?load current? above is sum of the load current of two internal voltage regulator. example circuit for regulator a/d, d/a converter characteristics for servo at ta = -40 ? c to +85 ? c, v dd 1 = 3.3v, dv ss = av ss = lrv ss = xv ss 1 = xv ss 2 = vv ss 1 = vv ss 2 = 0v parameter symbol condition min typ max unit resolution res 8 bit maximum input/output range vaio1 4/5 ? v dd 1 v minimum input/output range vaio2 1/5 ? v dd 1 v 1-bit d/a converter characteristics at ta = 25 ? c, v dd 1 = 3.3v, dv ss = av ss = lrv ss = xv ss 1 = xv ss 2 = vv ss 1 = vv ss 2 = 0v parameter symbol pin names conditions min typ max unit output level level lcho, rcho with a 1khz, 0db data signal 0.63 vrms total harmonics distortion thd+n lcho, rcho with a 1khz, 0db data signal, using the 20khz low-pass filter (built-in ad725d) 0.008 0.012 % dynamic range dr lcho, rcho with a 1khz, -60db data signal, using the 20khz low-pass filter and a-filter (built-in ad725d) 92 96 db signal to noise ratio s/n lcho, rcho with a 1khz, 0db data signal, using the 20khz low-pass filter and a-filter (built-in ad725d) 95 98 db cross talk ct lcho, rcho with a 1khz, 0db data signal, using the 20khz low-pass filter (built-in ad725d) 82 85 db note : measured in normal speed playback mode in sanyo?s 1-bit d/a converter block reference circuit. 1-bit d/a converter output reference circuit * same circuit need to be mounted both for two regulator pins. (no.42 and no.90) * the capacitor c1 must be greater than 50 ? f and low secure 50 ? f or more for low esr and the capacity value in the range of the operating temperature so that there is a possibility of the oscillation when the capacity value changes by the temperature change etc. (the recommended value is 100 ? f.) lc786960 100 f c1 dv dd dv ss dv dd 15 lc786960 rcho : same circuit as for lcho 10 f 100 f 1000pf 100k 680 lpf analog output left channel shibasoku co.,ltd. ad725d lrv dd lcho lrref rcho lrv ss
LC786960E no.a2080-18/24 oscillator example circuit for oscillator lc786960 rd2 c2 c2 c1 c1 rd1 xv ss 1 xout xin xv dd 1 xv dd 2 x16in x16out xv ss 2 (1) xin/xout: 12.0000mhz ? for system main clock, usb control ? recommended oscillator nihon dempa kogyo co., ltd. type recommended value nx5032ga rd1 = 0 ? , c1 = 4pf nx8045gb rd1 = 0 ? , c1 = 4pf (2) x16in/x16out: 16.9344mhz ? for cd control, audio control ? recommended oscillator murata manufacturing co., ltd. type recommended value cstce16m9v53-r0 rd2 = 0 ? , c2 = open cstcw16m9x51008-r0 rd2 = 0 ? , c2 = open cstls16m9x53-b0 rd2 = 0 ? , c2 = open nihon dempa kogyo co., ltd. type recommended value at51-cd2 rd2 = 0 ? , c2 = 8pf ? notes ? ? because the characteristics of oscillator could be change d according to the circuit boar d, ask evaluation with the individual original circuit board to the oscillator maker. ? the accuracy of 12mhz oscillator (xin /xout) must be in 500ppm when this oscillator clock is used for usb host function. ? concerning about internal circuit for xin/xout and x16in/x16out, refer to the ?analog pin internal equivalent circuits? section.
LC786960E no.a2080-19/24 analog pin internal equivalent circuits pin name (pin no.) equivalent circuit efmin (1) av dd av ss rfout (2) av dd av ss av dd av ss lpf (3) av dd av ss av dd av ss phlpf (4) av dd av ss ain (5) cin (6) bin (7) din (8) av dd av ss slciset (9) av dd av ss rfmon (10) av dd av ss av dd av ss continued to the next page.
LC786960E no.a2080-20/24 continued from the previous page. pin name (pin no.) equivalent circuit vref (11) av dd av dd av ss av ss jittc (12) av dd av ss ein (13) fin (14) av dd av ss te (15) av dd av ss av dd av ss tein (16) av dd av ss ldd (17) av dd av ss av dd av dd av ss lds (18) av dd av ss continued to the next page.
LC786960E no.a2080-21/24 continued from the previous page. pin name (pin no.) equivalent circuit fdo (21) tdo (22) sldo (23) spdo (24) av dd av ss av dd av ss pdout1 (26) vv dd 1 vv ss 1 vv dd 1 vv ss 1 pdout0 (27) vv dd 1 vv ss 1 vv dd 1 vv ss 1 pcncnt (28) vv dd 1 vv dd 1 vv ss 1 pckist (29) vv dd 1 vv ss 1 vv ss 1 xin (71) xout (72) xv dd 1 xin xout xv ss 1 xv dd 1 xv ss 1 continued to the next page.
LC786960E no.a2080-22/24 continued from the previous page. pin name (pin no.) equivalent circuit afilt (79) vv dd 3vv dd 3 vv ss 3 vv ss 3 x16out (92) x16in (93) xv dd 2 xin xout xv ss 2 xv dd 2 xv ss 2 lhco (96) rcho (98) lrv dd lrv ss lrv dd lrv ss lrref (97) lrv dd lrv ss lrv dd lrv ss slco (100) av dd av ss av dd av ss
LC786960E no.a2080-23/24 sample application circuit () () () () () () efmin slco to pickup to driver rfout lpf phlpf a b c d e f ld md vref (reference voltage) ain cin bin din vv dd 3 afilt vv ss 2 vv dd 2 uv dd udp udm slciset lc786960 rfmon vref d+ d- from/to usb-device jittc ein fin te tein ldd lds av ss av dd fdo tdo sldo spdo vv dd 1 pdout1 pdout0 pcncnt pckist vv ss 1 gnd v dd 1 * this sample circuit is only for cd servo block, each pll block and usb block. the value of each component needs to be adjusted under the target conditions. the circuit for cd servo shown above could be changed depending on the cd mechanism used. concerning to the application circuit for regulator, au dio dac and oscillator, refe r to the page 17 and 18 respectively.
LC786960E no.a2080-24/24 ps sanyo semiconductor co.,ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. regarding monolithic semiconductors, if you should intend to use this ic continuously under high temperature, high current, high voltage, or drastic temperature change, even if it is used within the range of absolute maximum ratings or operating conditions, there is a possibility of decrease reliability. please contact us for a confirmation. sanyo semiconductor co.,ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. it is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equ ipment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. this catalog provides information as of august, 2012. specifications and information herein are subject to change without notice.
